Hello! I'm Ananth
Welcome to my professional blog!
I’m Ananth, an Integrated Circuit (IC) design professional with more than a decade of experience in the semiconductor design industry. Throughout my career, I've developed a deep and broad expertise covering key aspects of IC design, including standard cell characterization, full chip floor planning, physical design, front-end integration, and tool/flow automation. My journey has allowed me to contribute significantly to leading companies in the field, such as NXP Semiconductors, Intel, Qualcomm, and AMD.
I hold a master’s degree in VLSI Design and Embedded Systems, which not only underpins my technical abilities but also enriches my approach to solving complex problems in innovative ways. My educational background and professional experience intertwine, enabling me to navigate the intricate dance of theoretical and practical challenges in semiconductor design.
On this blog, I aim to share insights, experiences, and reflections on the dynamic world of semiconductor technology. From in-depth articles on cutting-edge technologies to practical advice on navigating the challenges of the industry, I hope to provide valuable content that inspires and educates fellow engineers and enthusiasts alike.
Join me as we explore the fascinating, ever-evolving landscape of semiconductor technology together, pushing the boundaries and driving innovations that change the world.
EXPERIENCE
Member of Technical Staff
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Responsible for Synthesis, Timing closure and Clock Domain Crossing debug using industry standard tools like Fusion Compiler and Questa CDC
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Explore various Synthesis flow options to bridge the difference between Physical Design teams QoR with that of IP
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Independently able to evaluate and map RTL to Netlists and come up with possible timing improvements with RTL modifications
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Evaluate aspects of the process flow from high-level design to synthesis, timing, power and other Front End activities like Lint etc
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Scripting for automating day-to-day tasks for faster execution.
AMD Markham
Canada
June 2020-Present
Qualcomm India Private Ltd., India.
July 2017 – March 2020
Senior Engineer
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Planning, design, and implementation of assigned partitions from floor planning to DRV-clean GDS
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Floor planning using Cadence Innovus
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Placement and Route using IC Compiler 2
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Static timing analysis of hierarchical hard macros and generating timing-ECO collaterals using Tweaker
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Horizontal responsibilities: Fixing maxcap/maxtran/crosstalk violations
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Physical verification and cleaning all DRVs after metal filling to meet foundry requirements
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Design Automation: quick-fix automation to reduce turn-around time in crunch execution situations
Intel Technologies India Private Ltd., India
Aug 2015 - July 2017
SoC Design Engineer
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Planning, design, and implementation of assigned partitions from Verilog to timing closure.
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RTL to netlist generation using Design Compiler
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Placement and Route using IC Compiler 2
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Horizontal responsibilities: Quality checks like LEC, checking and validating constraints, Static Timing closure/Timing Analysis/Timing fixes
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Design Automation: quick-fix automation to reduce turn-around time in crunch execution situations
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Other responsibilities: Ramping up fresh recruits to desired execution level
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Testing and flushing out company-specific flows by collaborating with EDA engineers
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Planning component placement in Full Chip for consumption to partition owners
Logic libraries at NXP semiconductors, India
July 2014 - July 2015
Intern at Technology & Operations
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Automation and documentation of EDA view generation and validation flow of different EDA views
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Performing sign-off checks on standard cell libraries and verifying the fulfillment of customer specifications
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Implementing the characterization flow of standard cells in an automated format and understanding the dependency of various operations on this flow
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Schematic debugging and Layout optimization for standard cells
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Liberty modeling of cells including Level Shifters, isolation, always on cells etc
EDUCATION
Masters in Technology
Sep 2013 - June 2015
VLSI Design and Embedded Systems
RV College of Engineering, Bengaluru, India
Focus: Digital VLSI design
Bachelors in Technology
Aug 2009 - June 2013
Electrical and Electronics
RV College of Engineering, Bengaluru, India
Circuit design, Analog, and Digital Electronics
PROJECTS
TECHNICAL SKILLS
Familiar EDA Tools:
Design Compiler, Fusion Compiler, IC Compiler II, PrimeTime (Synopsys), Questa CDC, Cadence Virtuoso, Dorado Tweaker, Mentor Graphics Caliber
Scripting Languages:
TCL, C-Shell, Python
Design Skills:
Synthesizing RTL, Floor planning, P&R, STA, CDC, Digital circuit design, scripting to automate tasks, Design Rule Violation cleaning
PUBLICATIONS
ABSTRACT
The visually impaired are at a considerable disadvantage because they often lack the information for avoiding obstacles and hazards in their path. They have very little information on self-velocity, objects, direction - which is essential for travel. Previously developed navigation systems use costly equipment which is often not affordable by the common blind community. The navigation systems available are heavy and very complicated to operate. This research has been aimed at design and development of a smart and intelligent cane which helps in navigation for the visually impaired people. The navigator system designed will detect an object or obstacle using ultrasonic sensors and gives audio instructions for guidance. The signals from the ultrasound sensor are processed by a microcontroller in order to identify sudden changes in the ground gradient and/or an obstacle in front. The algorithm developed gives a suitable audio instruction depending on the duration of ultrasound travel which in turn is made available by an mp3 module associated with the system. This work presents a new prototype of navigation system on a cane which can be used as a travel aid for blind people. The product developed is light in weight, hence, does not cause fatigue to the user. This project is developed by keeping in view the affordability and reliability. An obstacle as close as 4cm can be detected by this module. A resolution of 15cm of obstacle distance has been designed and achieved. This system can also detect potholes on the path.